• DocumentCode
    516292
  • Title

    Deep Sub-Micron BICMOS Circuit Technology for Sub-10 ns ECL 4-Mb DRAMs

  • Author

    Kawahara, T. ; Kawajiri, Y. ; Kitsukawa, G. ; Sagara, K. ; Kawamoto, Y. ; Akiba, T. ; Kato, S. ; Kawase, Y. ; Itoh, K.

  • Author_Institution
    Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185 Japan
  • Volume
    1
  • fYear
    1991
  • fDate
    11-13 Sept. 1991
  • Firstpage
    29
  • Lastpage
    32
  • Abstract
    Alternatives for on-chip voltage limiters and direct sensing schemes were evaluated in terms of ease of design, voltage margins and speed. Based on these evaluations, a 0.3¿m ECL 4Mb BiCMOS DRAM was designed with a simulated access time of 7.8ns. It incorporates a voltage limiter featuring connection to VCC terminals, a BiCMOS output stage and use of a band-gap reference scheme, and a direct sensing scheme combined with a one-stage MOS amp. Through an analysis of access time dependence on device parameters, severe control of MOS transistor parameters proved to be a great importance in obtaining high speed DRAMs.
  • Keywords
    BiCMOS integrated circuits; CMOS technology; Design engineering; Laboratories; MOSFETs; Photonic band gap; Pulse amplifiers; Random access memory; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
  • Conference_Location
    Milan, Italy
  • Type

    conf

  • Filename
    5467896
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516292