Title :
Megacell - A Design System for CMOS VLSI
Author :
Williams, J.S. ; Pritchard, W.D. ; Clewett, D.R. ; Prior, B.J.
Author_Institution :
Plessey Research (Caswell) Limited, Caswell, Towcester, Northants, England.
Abstract :
A design system has been presented for the custom design of VLSI chips. The system is based on a cell library containing both simple gate and latch functions, and powerful parameterised cells, implemented on a fast 2.5 micron CMOS process. The combination of the library cells together with advanced simulation and layout CAD tools has produced a system capable of providing fast secure design of chips with complexities up to 30000 gates and beyond. Chips designed using the system are comparable in both speed and area with full custom designs.
Keywords :
Assembly; CMOS process; CMOS technology; Costs; Energy consumption; Logic design; Microcell networks; Microprocessors; Software libraries; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
Conference_Location :
Edinburgh, UK
