DocumentCode
516296
Title
Fully Digital Redundant Random Number Generator in CMOS Technology
Author
Acosta, Antonio J. ; Bellido, M.J. ; Valencia, Manuel ; Barriga, Angel ; Huertas, Jose Luis
Author_Institution
Depto. de Diseño de Circuitos Analógicos, Centro Nacional de Microelectrónica-Universidad de Sevilla, Edifico CICA, C/Tarfia s/n, 41012-Sevilla, SPAIN
Volume
1
fYear
1993
fDate
22-24 Sept. 1993
Firstpage
198
Lastpage
201
Abstract
This communication presents a new fully-digital redundant Random Number Generator. Its structure is that of a standard LFSR, with the difference that it includes one 1-bit ros-RNG in each basic cell. The design is modular, provides reasonable performances - simplicity, low cost and high speed -, it generates "truly" random sequences (i.e. aperiodic and unpredictable) and allows choosing random or pseudorandom sequences. Working like a "truly" random generator, the circuit produces random sequences from the first clock cycle, i.e., user must not wait a latency time to obtain a good sequence.
Keywords
CMOS digital integrated circuits; CMOS technology; Clocks; Costs; Delay; Hardware; Latches; Metastasis; Random number generation; Random sequences;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European
Conference_Location
Sevilla, Spain
Print_ISBN
2-86335-134-X
Type
conf
Filename
5467900
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