DocumentCode
516300
Title
A 34ns 16MbDRAM with controllable voltage down convertor
Author
Arimoto, Kazutami ; Hidaka, Hideto ; Hayashikoshi, Masanori ; Asakura, Mikio ; Fujishima, Kazuyasu ; Yoshihara, Tsutomu
Author_Institution
LSI R&D Lab. Mitsubishi Electric Corp., 4-1 Mizuhara, Itami, 664 Japan
Volume
1
fYear
1991
fDate
11-13 Sept. 1991
Firstpage
21
Lastpage
24
Abstract
This practical 16MbDRAM has a RAS access time (tRAC) of 34ns and a column address access time (tCAA) of 15ns and provides high reliability by the retrograded well structure. Two circuit techniques are developed to meet high speed operation: multi divided address decoding, and fully embedded sense amplifier driving. Additionally two circuit innovations enhance the operating margin and reduce the power dissipation: twisted bitline with double dummy canceling and hybrid voltage down converter (VDC) with accelerative life-test function.
Keywords
Acceleration; Capacitance; Circuit synthesis; Converters; Decoding; Drives; Large scale integration; Power dissipation; Research and development; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
Conference_Location
Milan, Italy
Type
conf
Filename
5467904
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