The Demonstration of Dislocation-Stress Memorization Technique Stressor on Si n-FinFETs

Author

Liao, M.-H. ; Chen, P.-G.

Author_Institution

Dept. of Mech. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

14

Issue

4

fYear

2015

fDate

Jul-15

Firstpage

657

Lastpage

659

Abstract

The dislocation stress memorization technique (D-SMT) stressor is demonstrated to boost the device performance on the Si three-dimensional (3-D) FinFET device. The larger channel stress and mobility enhancement ratio are observed in the narrower gate width device, due to the effect of triple crystal re-growth directions on the 3-D FinFET device. In this paper, ~33% mobility enhancement and ~23% Id,sat improvement on the Si FinFET device with W/L of 100/60 nm are achieved successfully with the implement of D-SMT stressor.

Keywords

MOSFET; carrier mobility; dislocations; elemental semiconductors; silicon; Si; channel stress; dislocation-stress memorization technique stressor; gate width; mobility enhancement; three-dimensional n-FinFET; triple crystal regrowth directions; Crystals; FinFETs; Logic gates; Performance evaluation; Silicon; Stress; Three-dimensional displays; Dislocation-stress memorization technique (D-SMT); FinFET; Si; Stressor; dislocation-stress memorization technique (D-SMT); stressor;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2015.2428698

Filename

7100928