• DocumentCode
    516325
  • Title

    Layout Generation for Multipliers in VLSI-Digital Signal Processing

  • Author

    Schuck, J. ; Glesner, M.

  • Author_Institution
    Technical University Darmstadt, Fachgebiet Halbleiter-schaltungstechnik, Schlossgartenstr. 8, D-6100 Darmstadt, FR Germany
  • fYear
    1984
  • fDate
    0-0 Sept. 1984
  • Firstpage
    165
  • Lastpage
    170
  • Abstract
    This paper presents a parameterization concept for the automatic layout generation of multipliers in digital signal processing. Based on a hierarchical cell design methodology the layout of parameterized two´s complement bit-parallel multipliers can automatically be generated according to any desired wordwidth of multiplicand and multiplier. Additionally the product can be rounded or truncated to either the longer or smaller wordwidth of the both input vectors.
  • Keywords
    Circuits; Clocks; Costs; Design methodology; Digital filters; Digital signal processing; Signal design; Signal generators; Signal processing; Silicon compiler;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
  • Conference_Location
    Edinburgh, UK
  • Type

    conf

  • Filename
    5467929
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516325