Layout Generation for Multipliers in VLSI-Digital Signal Processing

This paper presents a parameterization concept for the automatic layout generation of multipliers in digital signal processing. Based on a hierarchical cell design methodology the layout of parameterized two´s complement bit-parallel multipliers can automatically be generated according to any desired wordwidth of multiplicand and multiplier. Additionally the product can be rounded or truncated to either the longer or smaller wordwidth of the both input vectors.