An Analog Design Technique for Smart-Pixel CMOS Chips

This paper presents a systematic approach to design smart-pixel chips in standard CMOS technologies. These chips include light sensors together with parallel analog signal-processing circuitry, on the same silicon substrate. Light detection is made with vertical CMOS-compatible BJTs, which yield contrasts larger by an order of magnitude than conventional photodiodes. A Darlington structure is presented to further amplify the phototransistor current directly at the sensors plane. Pixel smartness is achieved by exploiting the Cellular Neural Network computation paradigm, incorporating at each pixel an analog computing unit (cell) which interacts with the cells of nearby pixels. Despite this local interaction, global tasks are performed on the two-dimensional signal, due to spatial propagation within the network. We propose a current-mode technique for CNN-based smart pixel chips and give measurements from a 1.6¿m CMOS 16×16 pixels prototype to calculate the number of connected pieces within each row of pixels of an input image.