Title :
High Speed 2um-gate CMOS Gate Arrays up to 10K-gates
Author_Institution :
Gate Array Eng. Dept. TOSHIBA. 72, Horicawa-Cho, Saiwai-Ku, Kawasaki, Japan
Abstract :
This paper descrives the current status of the high performance CMOS gate arrays, (1) a 2u-gate CMOS gate array series which has TTL speed and is available in the market, and (2) a sub-nanosecond 8K-gate CMOS/SOS gate array which is developed by using sub-2um design rule and cmpetes with ECL gate arrays.
Keywords :
CMOS process; Circuit optimization; Costs; Delay effects; Dry etching; Integrated circuit interconnections; Libraries; Logic functions; Macrocell networks; Planarization;
Conference_Titel :
Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
Conference_Location :
Edinburgh, UK
