DocumentCode
516347
Title
A 10-bit 5MS/s successive approximation ADC cell in 1.2μm CMOS
Author
Yuan, Jiren ; Svensson, Christer
Author_Institution
LSI design Center, IFM, Linköping University, S-581 83 Linköping, Sweden; The FERMI collaboration, CERN, Geneva, Switzerland
Volume
1
fYear
1993
fDate
22-24 Sept. 1993
Firstpage
9
Lastpage
12
Abstract
A 10-bit 5MS/s successive approximation ADC cell is presented. With a clock frequency of 70MHz, the sampling time is limited to 14nS, which is aimed for a parallel ADC array. A two-step principle based on unsymmetrical dualcapacitor charge-redistribution-coupling has been used. The comparator with the help of reset function presents a fast response to the successive comparison. The core of the ADC cell occupies an area of 0.6mm2 and consumes a power of 18mW while the chip consumes a total power of 32 mW.
Keywords
CMOS technology; Capacitors; Circuits; Clocks; Large scale integration; Parasitic capacitance; Sampling methods; Strips; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European
Conference_Location
Sevilla, Spain
Print_ISBN
2-86335-134-X
Type
conf
Filename
5467955
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