A Floating Point cell library for a 100MFLOPS Image Signal Processor

A new floating point macro cell library, suitable for logic synthesis of image signal processor, has been developed. A floating point Arithmetic Logic Unit(ALU), a floating point multiplier(MPY), an instruction RAM and a data register file are included in the library. The ALU and MPY can support not only IEEE754 floating point operations, but also fixed point operations and logical operations which are often used in image signal processing. They can operate at 33MHz clock cycle with three stage pipeline configuration. A new algorithm for calculation of absolute value is implemented in the ALU to get such a high speed operation. A new type of Vector Processor was synthesized with logic synthesis system. It has peak performance of 100MFLOPS at 33MHz, and it is suitable for large scale image processing, such as FFT, DCT, VQ and so on. High Speed 1.2 micron CMOS fabrication technology was used. In this paper, the details of the new algorithm used in the floating point ALU are discussed. Each component of the library and the synthesized Vector Processor is also described.