• DocumentCode
    516365
  • Title

    Design of Mixed-Mode Test Pattern Generator Structures

  • Author

    Dufaza, C. ; Voon, L. Lew Yan ; Cambon, G. ; Landrault, C.

  • Author_Institution
    Lab. d´´Autom. et de Microelectron. de Montpellier, Univ. of Montpellier II, Montpellier, France
  • Volume
    1
  • fYear
    1990
  • fDate
    19-21 Sept. 1990
  • Firstpage
    97
  • Lastpage
    100
  • Abstract
    The paper deals with mixed-mode test pattern generator structures (deterministic and pseudo-random) using modified Linear Feedback Shift Register structures. The method allows a substantial decrease of the length of the pseudo-random test sequence with a slight increase of the silicon area. A CMOS design validates the method.
  • Keywords
    CMOS logic circuits; automatic test pattern generation; circuit feedback; integrated circuit testing; logic testing; random sequences; shift registers; CMOS design; mixed-mode test pattern generator structures; modified linear feedback shift register structures; pseudo-random test sequence; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Sequential analysis; Tellurium; Test pattern generators; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
  • Conference_Location
    Grenoble
  • Print_ISBN
    2-86332-087-4
  • Type

    conf

  • Filename
    5467977
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516365