A 130 MHz 8-Bit CMOS Video DAC for HDTV Applications

Author

Fournier, J.M. ; Senn, P.

Author_Institution

Chemin du vieux chene, CNET, Meylan, France

Volume

1

fYear

1990

fDate

19-21 Sept. 1990

Firstpage

77

Lastpage

80

Abstract

A 130 MHz CMOS video DAC with a current output for HDTV applications will be described. In order to achieve monotonicity and a high speed performances current cell matrix configuration and a parallel decoding circuit with one stage latches have been used. P channel devices used as current sources insure a low noise level and a ground referenced voltage output in double adaptation load (38 ohms / 20 pF). The experimental results have shown that the maximum conversion rate is 130 MHz and the integral and differential linearity errors are less than 0.5 LSB. The maximum glitch energy is 50 pS.V. The DAC has been developed in a 1 μm digital/analog CMOS technology. It dissipates 150 mW at a 130 MHz conversion rate.

Keywords

CMOS analogue integrated circuits; CMOS logic circuits; digital-analogue conversion; high definition television; matrix algebra; video coding; 8-bit CMOS video DAC; HDTV; LSB; P channel device; cell matrix configuration; current source; differential linearity error; digital-analog CMOS technology; double adaptation load; frequency 130 MHz; integral linearity error; low noise level; maximum glitch energy; parallel decoding circuit; voltage output; word length 8 bit; CMOS technology; Circuits; Decoding; Feedback loop; Fluctuations; HDTV; Latches; Linearity; TV; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European

Conference_Location

Grenoble

Print_ISBN

2-86332-087-4

Type

conf

Filename

5467985