• DocumentCode
    516399
  • Title

    A CMOS 13 bits Cyclic RSD A/D Converter

  • Author

    Ginetti, B. ; Jespers, P. ; Vandemeulebroecke, A.

  • Author_Institution
    Université Catholique de Louvain - Laboratoire de microélectronique, Place du Levant, 3 1348 Louvain-la-Neuve, Belgium. Tel ++32 10 47 25 40 - Fax ++ 32 10 45 22 72
  • Volume
    1
  • fYear
    1991
  • fDate
    11-13 Sept. 1991
  • Firstpage
    245
  • Lastpage
    248
  • Abstract
    A differential cyclic RSD A/D converter is presented where the capacitors mismatch error is corrected without extra clock-phase or added hardware. An offset error cancellation based on the RSD properties is also included. The ADC achieves 13 bits linearity at 25kS/s and dissipates 40mW. Die area is 2.25 sqmm in a 3¿m CMOS process.
  • Keywords
    CMOS process; Capacitors; Circuits; Clocks; Error compensation; Error correction; Hardware; Linearity; Sampling methods; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
  • Conference_Location
    Milan, Italy
  • Type

    conf

  • Filename
    5468012
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516399