DocumentCode
516404
Title
A Compatible CMOS-JFET Pulse Density Modulator for Interpolative High-Resolution A/D Conversion
Author
Roettcher, U. ; Fiedler, H.-L. ; Zimmer, G.
Author_Institution
Fraunhofer Institute for Microelectronic Circuits and Systems, D-4100 Duisburg, Federal Republic of Germany
fYear
1985
fDate
16-18 Sept. 1985
Firstpage
89
Lastpage
96
Abstract
The analog part of a high-resolution A/D converter has been integrated in a compatible 3-5 ¿m CMOS-JFET technology. The circuit, which forms a pulse density modulator (PDM), can be operated at sample rates up to 12 MHz and reaches a SNR of 84 dB over a baseband of 20 kHz. This corresponds to approximately 14 bit A/D resolution.
Keywords
Active noise reduction; Clocks; Digital filters; Digital modulation; Noise shaping; Pulse amplifiers; Pulse circuits; Pulse modulation; Pulse width modulation converters; Quantization;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location
Toulouse, France
Type
conf
Filename
5468020
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