A High Speed 64K Bit CMOS RAM

The first memory of a high performances CMOS 64K family, an 8K×8 asynchronous static RAM has been developed, using a full CMOS 6 transistor memory cell approach, to reduce power consumption and enhance endurance in disturbed environment. New design techniques have been adopted to optimize both speed and power dissipation. Built on a self aligned CMOS technology with 1.5 micron design rules, the circuit reaches the size of 45 mm2 and achieves access time of 35 ns under typical conditions. To improve fabrication yield of the memory, redundancy assistance has been utilized, allowing correction of physical defects by column replacement.