A 256K CMOS EPROM

The need for high density, low power and fast CMOS EPROM has been established by the evolution of high performance circuits such as microprocessors. This paper will discuss A 256K CMOS EPROM utilizing 2 UM design rules technology. The word organization is 32K words X 8. The cell size is 54.4 UM2 and the die size is 29.6 MM2 including 4 extra rows and 2 extra columns. To reduce power consumption address transitions detections scheme is used; as a result power dissipation is less than 500 UW in stand-by mode and 150 mW at 4 MHZ in active mode. To minimize latch-up sensitivity the circuit is built on a P-type low resistivity substrate. The EPROM is fully compatible with existing NMOS circuit.