• DocumentCode
    516431
  • Title

    A 10 bits Pipeline Current Mode A/D Converter

  • Author

    Macq, D. ; Jespers, P.G.A.

  • Author_Institution
    Université Catholique de Louvain - Laboratoire de microélectronique, Place du levant, 3 B-1348 Louvain-La-Neuve, Belgium. Tel ++ 32 10 47 25 40, Fax ++ 32 10 47 86 67, E-Mail: macq@dice.ucl.ac.be
  • Volume
    1
  • fYear
    1993
  • fDate
    22-24 Sept. 1993
  • Firstpage
    5
  • Lastpage
    8
  • Abstract
    The Redundant Signed Digit (RSD) algorithm has been successfully applied to cyclic and pipeline analog to digital converters [1][2]. It is superior to the Convertional Restoring (CR) algorithm regarding cancellation of offset errors, speed and an additional bit. In this paper, we consider the advantages resulting from an implementation in a current-mode pipeline analog to digital converter.
  • Keywords
    Analog-digital conversion; CMOS technology; Capacitors; Chromium; Impedance; Operational amplifiers; Pipelines; Power supplies; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European
  • Conference_Location
    Sevilla, Spain
  • Print_ISBN
    2-86335-134-X
  • Type

    conf

  • Filename
    5468078
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516431