Cell Layout Library Parameterization

A method of layout parameterization is presented. Layout parameterization gives the possibility of varying layout rules and transistor dimensions in a layout without redesigning, while the topology and compactness of the layout remain intact. It provides flexibility with respect to layout language. The method presented here is based on vertical and horizontal scanning of a Manhattan type of layout. This results in a set of linear equations which is easily solvable. The unknowns of these equations are the dimensions of the mask details and the constants are the layout rules and/or transistor dimensions. The equations are solved by a modified Gaussian solution procedure. Cell hierarchy is supported by introducing dependent dimensions of cells. The scanning procedure also yields the generation of a new, parameterized layout description. Combining this description and the solutions of the equations results in a normal, fixed value layout description.