• DocumentCode
    516461
  • Title

    A High-Speed Adder in Cryogenic N-MOS

  • Author

    Glories, P. ; Boudou, A. ; Ecuyer, Y.L. ; Leclaire, P. ; Chantraine, P.

  • Author_Institution
    BULL, Direction Recherche et Technologie Groupe, Circuits Intÿgrés, Av. Jean Jaurÿs, 78 340, Les Clayes sous Bols, France
  • fYear
    1985
  • fDate
    16-18 Sept. 1985
  • Firstpage
    381
  • Lastpage
    384
  • Abstract
    Low temperature MOS devices (77K) present significant gain in speed and density for a low technological cost. We report results concerning a three bits adder fabricated with an adapted cryogenic N-MOS process, using Argon-implanted polysilicon loads; the maximum measured frequency was 405 MHz for a 28 mW power consumption, with 2.4¿ design rules.
  • Keywords
    Adders; Circuits; Cryogenics; Energy consumption; Gallium arsenide; Logic devices; MOS devices; Temperature; Threshold voltage; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
  • Conference_Location
    Toulouse, France
  • Type

    conf

  • Filename
    5468167
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516461