Low-Power GaAs ICs

For high-speed GaAs integrated circuits ICs) of LSI complexity to be realized, a technology with low-power dissipation with maintaining circuit speed must be used. Previous GaAs research at Honeywell has focused on the conventional depletion-mode GaAs MESFET, which is capable of only MSI circuits [1-2]. Depletion-mode gate arrays using buffered FET logic (BFL) have demonstrated 1.3 mW at 740 ps per cell [3]. Enhancement-mode and depletion-mode gate arrays have shown gate delays of 42 ps at 500 ¿W. The enhancement-mode MESFET self-aligned gate process has dononstrated numerous LSI circuits, including a 2K gate array [4], a 16 × 16-bit multiplier [5], and a 16K-bit static RAM [6]. This paper describes the design fabrication and circuit results using the self-aligned gate MESFET technology for low-power depletion-mode Schottky diode FET logic (SDFL) and very low-power enhancement-mode direct-coupled FET logic (DCFL). Figure 1 is a photograph of the GaAs self-aligned test chip with the 2K-cell SDFL gate array. This self-aligned gate process is capable of fabricating both the high-transconductance depletion- and enhancement-mode devices necessary for LSI circuits. Transconductances of the enhancement-mode MESFET as high as 216 mS/mm are obtained for 0.7-¿m gates and 170 mS/mm for 1-¿m gates with a corresponding output conductance of 8 mS/mm. This low-output conductance is achieved without the use of "T" gate structures but with the proper choice of implant parameters. For deplection-mode circuits, SDFL operating at 108 ¿W per gate has shown propagation delays of 1.6 ns.