Title :
Hierarchical Design Verifications based upon a Topological Access to Circuit Data
Author :
Berger, J. ; Mazare, G.
Author_Institution :
Laboratoire de Genie Informatique de l´´IMAG/CNRS, BP 68 38402 St Martin d´´heres cedex FRANCE
Abstract :
This paper describes a method that uses design hierarchy, signal connectivity information, and topological data retrieval to perform incremental design rule checking, and electrical node extraction.
Keywords :
Algorithm design and analysis; Buildings; Circuits; Design methodology; Information retrieval; Signal design; Testing; Tiles; Tree data structures; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
Conference_Location :
Delft, The Netherlands
