DocumentCode
516512
Title
Area Optimized MOS Circuit Generation using the Circuit Synthesis Program MOSYN-2
Author
Asada, K. ; Mavor, J.
Author_Institution
Department of Electronic Engineering, The University of Tokyo, The King´´s Building, Edinburgh EH9 3JL, The United Kingdom
fYear
1986
fDate
16-18 Sept. 1986
Firstpage
71
Lastpage
73
Abstract
An area optimized circuit synthesis scheme for MOS LSI logic is presented. The optimum circuit is selected out of multiple circuits based on three kinds of area estimation index numbers for circuit topologies. The circuits are generated by a circuit synthesis program MOSYN-2 from a logic specification. These area estimation index numbers can be used for both random and gate matrix layout methods. The scheme is demonstrated by an ALU circuit generation.
Keywords
Algorithm design and analysis; Automatic logic units; Circuit synthesis; Circuit topology; Input variables; Logic circuits; Logic design; Logic functions; Optimization methods; Random number generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
Conference_Location
Delft, The Netherlands
Type
conf
Filename
5468299
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