DocumentCode :
516531
Title :
A Realtime Image Signal Processor (Version II) with Micro-Programmable and Expandable Architecture
Author :
Aono, Kunitoshi ; Maruyama, Masakatsu ; Mori, Toshiki ; Yamada, Haruyasu ; Hataya, Kinji
Author_Institution :
Semiconductor Research Center, Matsushita Electric Co., Ltd., 3-15 Yagumo-Nakamachi, Moriguchi, Osaka, 570 Japan
fYear :
1986
fDate :
16-18 Sept. 1986
Firstpage :
98
Lastpage :
100
Abstract :
A micro-programmable Realtime Image Signal Processor (RISP-version II) has been developed fabricated in the 1.5-¿m bipolar technology. The RISP-II, designed for use in the local image processing, has attained the per-chip processing speed as high as 100 MIPS. The multi-chip processing has been realized by added features: parallelism with the local image register, and pipelining with the pipeline register. Therefore, the execution speed can easily double or more when two or more RISP-IIs are adopted, and the local window can be enlarged simultaneously.
Keywords :
Arithmetic; Digital images; Gold; Image edge detection; Image processing; Image sampling; Pipeline processing; Pixel; Registers; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
Conference_Location :
Delft, The Netherlands
Type :
conf
Filename :
5468320
Link To Document :
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