Title :
Architecture of a Monolithic Digital Signal Processor with a Novel Control Flow Concept
Author_Institution :
Lehrstuhl fuer Technische Elektronik, University of Erlangen-Nuremberg, Cauerstr. 9, D 8520 Erlangen, Germany
Abstract :
The architecture of a monolithic digital signal processor for general purpose applications is presented. The extreme usage of pipelining permits an instruction cycle time of 15ns in CMOS-technology, thereby increasing flexibility. Problems arising from the pipeline length are discussed, and solutions are explained. A simulator and some test circuits have been implemented showing a significant increase in performance compared to contemporary designs.
Keywords :
Arithmetic; Circuit simulation; Circuit testing; Decoding; Digital signal processors; Pipeline processing; Process design; Signal design; Signal processing; Signal processing algorithms;
Conference_Titel :
Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
Conference_Location :
Delft, The Netherlands
