Automatic Design of Exhaustively Self-Testing VLSI Circuits

A procedure for designing built-in test logic for exhaustively self-testing circuits is presented. A unique feature of the presented method is that all decisions about the organization of the built-in self-test logic are based on a high-level circuit description and, therefore, can be made early in the design cycle. This attribute along with a low computational complexity make the proposed technique very attractive for application in a silicon compilation environment.