DocumentCode :
516596
Title :
A SEM-Based Workstation for Desigh Validation
Author :
Vernay, Y.-J. ; Mignone, R. ; Rivoire, P.
Author_Institution :
Centre National d´´Etudes des Télécommunications, BP 98, Chemin du Vieux Chêne, 38243 MEYLAN Cedex, France
fYear :
1986
fDate :
16-18 Sept. 1986
Firstpage :
179
Lastpage :
180
Abstract :
This paper describes a workstation for circuit testing based upon a Scanning Electron Microscope (SEM) tester and which is part of a complete CAD tool. A major factor of the system is its ability to be interfaced to existing testers and to existing circuit description formats.
Keywords :
Circuit testing; Computer graphics; Computer networks; Databases; Design automation; Scanning electron microscopy; Software testing; System testing; Time measurement; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
Conference_Location :
Delft, The Netherlands
Type :
conf
Filename :
5468395
Link To Document :
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