Title :
Architecture and Design Methodology of 32KByte Integrated Cache Memory
Author :
Nogami, Kazutaka ; Sakurai, Takayasu ; Sawada, Kazuhiro ; Shirotori, Tsukasa ; Takayanagi, Toshinari ; Iizuka, Tetsuya ; Maeda, Takeo ; Matsunaga, Junichi ; Fuji, Hiromichi ; Maeguchi, Kenji ; Kobayashi, Kiyoshi ; Ando, Tomoyuki ; Hayakashi, Yoshiki ; Miy
Author_Institution :
TOSHIBA Corporation, 1, Komukai-Toshiba-cho, Saiwai-ku, Kawasaki, 210 Japan
Abstract :
The architectural aspects of a newly deveoped integrated cache memory is described in this paper, which includes 32Kbyte DATA memory with a typical ADDRESS to HIT delay, the largest memory size and fastest speed ever reported as an integrated cache memory[1]. The device integrates data/instruction memory, tag memory and a comparator on a chip. It serves as a cache memory of several host MPUs by aluminum masterslice.
Keywords :
Automatic control; Cache memory; Circuits; Control systems; Data engineering; Design methodology; Logic devices; Microcomputers; Pins; Technical Activities Guide -TAG;
Conference_Titel :
Solid-State Circuits Conference, 1988. ESSCIRC '88. Fourteenth European
Conference_Location :
Manchester, UK
