Title :
Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAMs
Author :
Sakata, Takeshi ; Horiguchi, Masashi ; Aoki, Masakazu ; Itoh, Kiyoo
Author_Institution :
Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185 Japan
Abstract :
Two-dimensional power-line selection scheme for an iterative CMOS circuit block, is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks of two-dimensional arrangement and selectively energized by two-dimensional power-line selection. The scheme combined with dual word-line structure permits a drastic active current reduction to one sixteenth, from 363 mA to 22 mA, for a 16-Gb DRAM.
Keywords :
Degradation; Driver circuits; Laboratories; MOSFETs; Random access memory; Subthreshold current; Switches; Threshold voltage; Turning;
Conference_Titel :
Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European
Conference_Location :
Sevilla, Spain
Print_ISBN :
2-86335-134-X
