SLOCOP : A Timing Verification Tool for Synchronous CMOS Logic

In this paper, a new, accurate method for timing characterisation of synchronous CMOS circuits, described at transistor level, is presented. It is implemented in a computer program SLOCOP. SLOCOP first performs a knowledge based partitioning of the circuit into registers and combinational subcircuits, verifies high level timing rules (clock phasing) and finally detects longest signal propagation paths, with an accuracy comparable to device level simulation. Besides the delays of the critical paths, SLOCOP generates test patterns that activate these paths. The test pattern generation algorithm eliminates false paths and allows the designer to check the delay by an overall simulation. For delay calculation, local simulation is done with accurate SPICE-like transistor models. Critical paths are graphically displayed using hierarchical backannotation to a schematic. Deviations between estimated and real (simulated) delays are typically within 5% for static CMOS circuits. Pass transistor logic may give larger errors which remain however within 10%.