Title :
Statistical Modeling and Simulation for DAC Design
Author :
Conroy, C.S.G. ; Lane, W.A.
Author_Institution :
National Microelectronics Research Centre, University College, Lee Maltings, Prospect Row, Cork City, Ireland
Abstract :
A Monte-Carlo approach has been applied to the estimation of yield of CMOS Digital-to-Analog Converter circuits as a design optimization tool. Parasitic circuit elements are included. A components of variance model is used to describe the multilevel variability of the resistors. The dependence of yield on the nominal values and the variances of circuit parameters has been examined. Test structures have been fabricated to investigate further the statistical distributions of DAC circuit elements.
Keywords :
Circuit simulation; Circuit testing; Design optimization; Digital-analog conversion; Integrated circuit modeling; Resistors; Semiconductor device modeling; Statistical analysis; Statistical distributions; Yield estimation;
Conference_Titel :
Solid-State Circuits Conference, 1986. ESSCIRC '86. Twelfth European
Conference_Location :
Delft, The Netherlands
