Title :
A 32ns 64Mb DRAM with Extended Second Metal Line Architecture
Author :
Miyamoto, Hiroshi ; Morooka, Yoshikazu ; Furutani, Kiyohiro ; Yasuda, Kcn-ichi ; Kikuda, Shigcru ; Tsukikawa, Yasuhiko ; Arima, Hideaki ; Ozaki, Hideyuki ; Yoshihara, Tsutomu
Author_Institution :
LSI Lab., Mitsubishi Electric Corp., 4-1 Mizuhara, Itami, 664 Japan
Abstract :
This paper proposes a new array architecture named extended second metal line (ESL) architecture, in which second metal line is used as not only power lines for distributed sense-amp drivers but global data-buses in the memory array. The self-recovering Vpp generator for output driver is further described to ensure the output high level in fast column access modes. By using the proposed array and circuit techniques in a 64Mb DRAM, fast RAS access time of 32ns has been achieved.
Keywords :
Capacitance; Circuit synthesis; Delay; Distributed amplifiers; Driver circuits; Large scale integration; Power dissipation; Power generation; Random access memory; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 1993. ESSCIRC '93. Nineteenth European
Conference_Location :
Sevilla, Spain
Print_ISBN :
2-86335-134-X
