Title :
A Comparative Analysis of the Coverage of Voltage and IDDQ Tests of Realistic Faults in a CMOS Flip-flop
Author :
Samsom, S.M. ; Baker, K. ; Thijssen, A.P.
Author_Institution :
Philips Research Laboratories, P.O.Box 80000, 5600 JA Eindhoven, The Netherlands
Abstract :
A defect-oriented, inductive method is used to derive an accurate and complete set off faults for a CMOS flip-flop. IDDQ and voltage testing are investigated. Results of fault simulations show that an IDDQ based test strategy is the most economical. Also design-for-testability proposals are discussed to increase the fault coverage of IDDQ tests.
Keywords :
CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Flip-flops; Laboratories; Production; Proposals; Sequential circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1994. ESSCIRC '94. Twentieth European
Conference_Location :
Ulm, Germany
Print_ISBN :
2-86332-160-9
