• DocumentCode
    516661
  • Title

    Latched-Flip-Flops - a new scantest-methodology

  • Author

    Scheuermann, K. ; Ebert, H.

  • Author_Institution
    Philips Kommunikations Industrie AG, Thurn-und-Taxis Str. 10, D-90327 Nÿrnberg
  • fYear
    1994
  • fDate
    20-22 Sept. 1994
  • Firstpage
    232
  • Lastpage
    235
  • Abstract
    This paper describes a new scantest-approach which defines a design-independent standardized test-protocol. It guarantees a short time for test-preparation and testerrun. The described latched-flip-flop solves almost all problems in testing multiple clock-designs with an acceptable gate-overhead. By using latched-flip-flops it is possible to implement BIST and INTEST without taking different clocksystems into consideration.
  • Keywords
    Added delay; Automatic test pattern generation; Built-in self-test; Clocks; Control systems; Master-slave; Modems; Switches; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1994. ESSCIRC '94. Twentieth European
  • Conference_Location
    Ulm, Germany
  • Print_ISBN
    2-86332-160-9
  • Type

    conf

  • Filename
    5468492
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516661