A 40Mbit/s Soft-Output Viterbi Decoder

Soft output decoding has evolved as a key technology for new error correction approaches with unprecedented performance as well as for improvement of well established transmission techniques. In this paper we present, to the best of our knowledge, the first high speed VLSI implementation of the soft output Viterbi algorithm, a low complexity soft output algorithm. The 43mm² chip is designed for a 16 state convolutional code, and tested samples achieved a throughput of 50 Mbit/s. The chip is roughly twice as big as a Viterbi decoder without soft outputs. It is thus shown with the design that transmission schemes using soft output decoding can be considered practical even at very high throughput.