General Algorithm for a Simplified Addition of 2´s Complement Numbers in Multipliers

Two algorithms for both a simplified carry save and carry ripple addition of 2´s complement numbers as implemented in multipliers are presented. The algorithms form the partial products so that they have exclusively positive coefficients which leads to the elimination of the common sign bit extension. This results in a reduction of the circuit area by up to six full adders per row of adders when partial products are added in a Wallace or N/2 tree. Furthermore, the capacitive load of the intermediate sum and carry sign bit signals decreases by up to a factor of seven which leads to an appropriate reduction of delay.