Internal State Assignment for Two-Level Hazard-Free Asynchronous Implementation

An internal state assignment for hazard-free circuit design without additional delays is presented. Each logic element is considered as a composition of a logic function and a delay. It is supposed no input variable hazards (only one input variable changes at the time) and race-free assignment using Tracey\´s method. The race-free code expansion procedure 1) to design covering implicants avoiding 1-hazards and 2) to "delay" internal variable changes within flow table non-essential and essential configurations is offered.