A High Level Design Methodology for the Power Optimisation of Highly Integrated Receiver Architectures

The rapidly changing world of wireless communications, requires the implementation in a short time of new receiver architectures operating at a higher frequency, a lower operating voltage and a lower power consumption. The evaluation of the power consumption of a given receiver topology is today only done at the lowest design levels. This paper presents a systematic approach for the high-level design and automated optimization for minimum power consumption of analog receiver front-ends. The presented method is based on a new power spectral density simulation method, working with the formula manipulation of rational polynomials, placed in a simulated annealing optimization loop. A C++ implementation of this high-level design methodology is presented and discussed.