A high speed 0.7μm CMOS PLL circuit for clock/data recovery in interconnection systems

In this paper a CMOS PLL circuit realised for clock and data recovery in interconnection systems is presented. The purpose of this clock recovery PLL is to generate a clock with frequency and phase locked to the input NRZ data, in order to sample them in the optimum point. The topology of the circuit is characterised by two loops, one for the phase lock, the second for a frequency aided acquisition system. A full custom approach has been used in the PLL implementation to obtain an high operation speed. Its compact implementation allows the PLL blocks to be included in different CMOS ICs as library elements. An operating range of 150-550 Mbit/s has been obtained.