A Low-Power True Single Phase Clocked (TSPC) Full-Adder

A TSPC full-adder circuit containing only 6 clock transistors and thus consuming significantly less power than recently published full-adders has been designed and characterized by simulation. It is composed of 36 transistors and consumes 220 ¿W @100 MHz when connected to a 5 V power supply, using a 0.8 ¿m standard CMOS process technology. This considers all parasitic capacitances as well as the power needed for clocking. Although minimum size transistors are used exclusively, and precharge gates are avoided in order to minimize power consumption, the operating frequency may be raised up to 290 MHz.