Title :
Low-Power Logic Styles : CMOS vs CPL
Author :
Zimmermann, Reto ; Gupta, Rajiv
Author_Institution :
Integrated Systems Laboratory, Swiss Federal Institute of Technology, CH-8092 Zÿrich, Switzerland
Abstract :
Recently reported logic style comparisons based on full-adder circuits showed complementary pass-transistor logic (CPL) to be much more power efficient than conventional CMOS. New comparisons performed on more efficient CMOS circuit implementations and a wider range of different logic cells and by using realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, power dissipation, and power-delay (PT) products.
Keywords :
CMOS logic circuits; Capacitance; Circuit simulation; Combinational circuits; Delay; Logic circuits; Logic design; Logic devices; Power dissipation; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1996. ESSCIRC '96. Proceedings of the 22nd European
Conference_Location :
Neuchatel, Switzerland
Print_ISBN :
2-86332-197-8
