Title :
Sense-Amplifier-Merged Comparator and Selector Scheme for BiCMOS Cache Memories
Author :
Suzuki, Makoto ; Tachibana, Suguru ; Ohkubo, Norio ; Yano, Kazuo ; Hiraki, Mitsuru ; Hanawa, Makoto ; Shukuri, Shohoji ; Hirao, Mitsuru ; Ohki, Nagatoshi ; Nishida, Takashi ; Seki, Koichi
Author_Institution :
Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan
Abstract :
A novel circuit technique called a sense-amplifier-merged comparator and selector scheme for BiCMOS cache memories is developed. An ECL gate with an active PMOS load circuit is proposed and effectively applied in this scheme. The inherent high-speed and low-power nature of the circuit scheme is described in conjunction with attained performance of a test chip, which is designed and fabricated using a self-aligned 0.3 ¿m BiCMOS technology.
Keywords :
BiCMOS integrated circuits; Cache memory; Capacitors; Chirp modulation; Delay effects; Frequency modulation; Linearity; Switching circuits; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
Conference_Location :
Milan, Italy
