• DocumentCode
    516855
  • Title

    Versatile CMOS Rate Multiplier/Variable Divider

  • Author

    den Dulk, Richard C. ; Stuyt, Jan J. ; Regenbogen, Lodewijk K. ; Croes, Rob C.

  • Author_Institution
    Dept. of Electr. Eng., Delft Univ. of Technol., Delft, Netherlands
  • fYear
    1982
  • fDate
    22-24 Sept. 1982
  • Firstpage
    145
  • Lastpage
    148
  • Abstract
    This paper presents a CMOS universal programmable rate multiplier/variable divider that generates optimally spaced output signals. The chip is designed using an industrial polysilicon gate CMOS process with a 4 μm gate length and local oxidation.
  • Keywords
    CMOS integrated circuits; frequency dividers; frequency multipliers; polysilicon gate CMOS process; size 4 mum; variable divider; versatile CMOS rate multiplier; CMOS integrated circuits; CMOS process; CMOS technology; Digital circuits; Frequency synthesizers; Laboratories; Oxidation; Pulse generation; Signal generators; Space technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1982. ESSCIRC '82. Eighth European
  • Conference_Location
    Brussels
  • Type

    conf

  • Filename
    5468858
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516855