• DocumentCode
    516888
  • Title

    Expectable Performances of Short Channel NMOS Technologies

  • Author

    Gautier, J. ; Giffard, B. ; Guerin, M. ; Guegan, G.

  • Author_Institution
    L.E.T.I. - COMMISSARIAT A L´´ENERGIE ATOMIQUE, 85 X - 38041 - GRENOBLE CEDEX - FRANCE
  • fYear
    1983
  • fDate
    21-23 Sept. 1983
  • Firstpage
    163
  • Lastpage
    166
  • Abstract
    A program for automatic scaling of technologies is presented. Its purpose is to determine expectable performances of submicron Enhancement-Depletion NMOS technologies. A ripple carry adder test circuit has been realized to show that high performances are really usable in complex circuits. Thus with ten logic layers and an average Fan Out about 3, this adder circuit can work with a clock frequency of 420 MHz for a power consumption of 120 mW.
  • Keywords
    Adders; Circuit noise; Circuit testing; Clocks; Design optimization; Logic testing; MOS devices; Noise level; Performance evaluation; Propagation delay;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
  • Conference_Location
    Lausanne, Switzerland
  • Print_ISBN
    2-88074-021-5
  • Type

    conf

  • Filename
    5468896
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516888