Title :
Automatic Generation of Metal Oriented Layout for CMOS Logic
Author :
Piguet, C. ; Bertarionne, M.
Author_Institution :
Centre Electronique Horloger S.A., Neuchâtel, Switzerland
Abstract :
In order to decrease the development time and cost of integrated CMOS circuits, we present a design methodology based on the following characteristics: - direct translation of logic equations into symbolic layout - metal oriented symbolic layout - automatic generation of layout based on the assembly of microcells.
Keywords :
Automatic logic units; CMOS logic circuits; Character generation; Design automation; Design methodology; Equations; Layout; Logic design; MOSFETs; Microcell networks;
Conference_Titel :
Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
Conference_Location :
Lausanne, Switzerland
Print_ISBN :
2-88074-021-5
