On Chip Bias Generation for 5-Volt N-Channel MOS

Many modern 5V n-channel MOS processes have been designed to operate with a negative bias supply; a typical value is -2.5V. The Post Office 5V process requires a bias voltage of this magnitude, and to eliminate the need for the user to provide this bias supply it Is intended to provide an on-chip bias generator on all our future 5V LSI circuits. This paper will discuss our current thinking on bias generator design. Observations on the charge pump showed that the inclusion of the additional transistor T2 in Figure 2 gives a very worthwhile improvement in generated bias voltage. Both simulation and observed results showed that a Schmitt trigger type of oscillator was less tolerant of processing and supply voltage variations and additionally was more difficult to interface with the driver stages. The inverter ring oscillator proved to be a very efficient design both in area and power consumption. A complete bias generator, using the circuit of Figure 4 consumed 8 mW at 5 volts supply and is our preferred design.