Title :
Clocked Logic Configurations for High Speed Serial Data
Author_Institution :
University of Essex, U.K.
Keywords :
Clocks; Digital signal processing; Feedback; Logic arrays; Logic circuits; Propagation delay; Signal design; Stress; Switches; Timing;
Conference_Titel :
Solid State Circuits Conference - ESSCIRC 79, Fifth European
Conference_Location :
Southampton, UK
Print_ISBN :
0-85296-208-8
