Content Addressable Memory with Parallel Write Facilities

The increasing capabilities of todays LSI-technology have raised the interest in complex building blocks (RAM, ROM, microprocessor, etc.) for use in large electronic systems. We believe that a content addressable memory (CAM, refs 1-3) is such a standard function too. Much information-processing is performed by means of tables. By using a CAM, table searching can be done efficiently in the memory, thus moving some software routines to the hardware level. Yet there is no generally accepted standard for a CAM. The existing CAM chips generally contain only an array of memory cells without any control circuitry. Moreover reading and writing is done in the same way as in a RAM : the information must be accompanied by the address of the physical location to be used. In this paper we present a new approach to the concept of a CAM, suitable for integration.