Title :
2 GHz Logic based on a 5 GHz fT Process
Author :
Kitchin, M. ; Walsh, P.S. ; Ward, P.J.
Author_Institution :
Allen Clark Res. Centre, Plessey Co. Ltd., Towcester, UK
Abstract :
The first optimised designs for the high speed variant of Plessey´s Bipolar Process III have been evaluated. Process features will be followed by performance details for a 500 pSec ECL gate, a ring oscillator and divider circuits.
Keywords :
dividing circuits; logic circuits; logic design; logic gates; oscillators; ECL gate; Plessey bipolar process III; divider circuits; frequency 2 GHz; frequency 5 GHz; ring oscillator; time 500 ps; Circuits; Delay; Design optimization; Doping profiles; Epitaxial layers; Heat treatment; Ion implantation; Logic arrays; Packaging; Ring oscillators;
Conference_Titel :
Solid State Circuits Conference, 1976. ESSCIRC 76. 2nd European
Conference_Location :
Toulouse
