DocumentCode :
517049
Title :
Stacked I2L Circuit
Author :
Nagata, M. ; Kaneko, K. ; Okabe, T.
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
fYear :
1976
fDate :
21-24 Sept. 1976
Firstpage :
60
Lastpage :
61
Abstract :
A "stacked circuit" with T2L configuration is discussed which cuts effective power dissipation to one-third that of conventional T2L circuits.
Keywords :
transistor-transistor logic; effective power dissipation; stacked T2L circuit; twin-transistor-injection-logic circuit; Circuits; Current supplies; Energy consumption; Isolation technology; Laboratories; Logic functions; Power dissipation; Resistors; Stacking; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference, 1976. ESSCIRC 76. 2nd European
Conference_Location :
Toulouse
Type :
conf
Filename :
5469092
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=517049
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