Title :
A Defect-Tolerant Design for Full-Wafer Memory LSI
Author :
Ueoka, Yasushige ; Minagawa, Chozaburo ; Oka, Masahiko ; Ishimoto, Akiteru
Author_Institution :
Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corp., Musashino, Tokyo 180, Japan
Abstract :
A defect-tolerant design method realizing full-wafer integration was experimentally verified. The method features automatic inspection, detection and shift or selection. A 1.5 Mbit frame-memory on a 4 inch silicon wafer (64-color 512×512-dot plane) was designed and implemented.
Keywords :
Design methodology; Hamming distance; Inspection; Integrated circuit interconnections; Laboratories; Large scale integration; Parity check codes; Silicon; Switches; Telegraphy;
Conference_Titel :
Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
Conference_Location :
Lausanne, Switzerland
Print_ISBN :
2-88074-021-5
